As semiconductor devices, including logic devices and memory devices, scale to smaller dimensions, device patterning increasingly limits the ability to harness the improvements potentially resulting from smaller size. For example, three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET) impose severe geometrical constraints for forming contacts to the source/drain (S/D) region of a transistor. Some current techniques for forming finFET exhibit a small process window for forming a self-aligned contact to the source/drain region. In known finFET devices using replacement gate scheme, for example, shorting of a S/D contact to a given transistor gate may take place because of the inherent gate height variation between different transistors distributed across a semiconductor substrate (wafer). One cause of this variation may be the multiple chemical mechanical polish (CMP) operations, such as four or more CMP operations, used to form replacement gate transistors. While the use of a narrower S/D contact between adjacent gate structures may tend to lessen the chance of exposing a transistor gate during CMP or other processing, this approach generates smaller contact area and thus higher contact resistance in the transistor device.
With respect to these and other considerations, the present disclosure is provided.